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Si4322
Bit 5-4 < rl1:rl0 >:
Limit the value of the frequency offset register to the following values:
rl1
0
rl0
0
Max dev [fres]
No restriction
0
1
1
1
0
1
±4
±2
±1
fres:
868MHz band: 20 kHz
915MHz band: 20 kHz
Bit 7-6 < a1:a0 >:
Automatic operation mode selector:
a1
a0
BASEBAND SIGNAL IN
0
0
1
1
0
1
0
1
Auto mode off (Strobe is controlled by uC)
Runs only once after each power-up
Keep the f offset only during receiving (VDI=high).
Keep the f offset value
ATGL**
ASAME***
10MHz CLK.
/4
0
1
M
U
X
CLK
DIGITAL LIMITER
4 BIT
OFFS
<3:0>
12 BIT
fi (bit2)
en (bit0)
FINE
ENABLE CALCULATION
DIGITAL AFC
CORE LOGIC
4
IF IN>MaxDEV THEN
OUT=MaxDEV
4
FREQ.
OFFSET
REGISTER
ADDER
Fcorr<11:0>
to synthesizer
VDI*
au (bit6,7)
Power-on reset
(POR)
rl1,0 (bit4,5)
st (bit3)
oe (bit1)
F<11:0>
from Frequency
Setting Command
AUTO OPERATION
used in auto
operation
mode
RANGE LIMIT
STROBE
OUTPUT ENABLE
IF IN<MinDEV THEN
OUT=MinDEV
ELSE
OUT=IN
strobe
output enable
CLK CLR
NOTE:
* VDI (valid data indicator) is an internal
signal of the controller.
See the Receiver Setting Command for detailes.
** ATGL: toggles in each measurement cycles.
*** ASAME: logic high when the result is stable.
In automatic operation mode (no strobe signal is needed from the microcontroller to update the output offset register), the AFC circuit is
automatically enabled when VDI indicates a potential incoming signal during the whole measurement cycle and the circuit measures the
same result in two subsequent cycles.
There are three operation modes, example from the possible application:
1, ( a1 =0, a0 =1) The circuit measures the frequency offset only once after power up. This way, the extended TX/RX maximum distance can
be achieved. In the final application when the user is inserted the battery the circuit measures and compensate the frequency offset caused
by the crystal tolerances. This method enables to use cheaper quartz in the application and provide quite good protection against locking in
an interferer.
2a, ( a1 =1, a0 =0) The circuit measures automatically the frequency offset during an initial low data rate pattern – easier to receive – (i.e
00110011) of the package and change the receiving frequency according that. The further part of the package can be received by the
corrected frequency settings.
2b, ( a1 =1, a0 =0) The transmitter must transmit the first part of the packet with a step higher deviation and later it is possible to reduce it.
In both cases ( 2a and 2b ) when the VDI indicates poor receiving conditions (VDI goes low) the output register is automatically cleared. It is
suggested to use when one receiver receives signal from more than one transmitter.
3, ( a1 =1, a0 =1) It is similar to the 2a and 2b modes, but 3 is suggested to use when a receiver operates with only one transmitter. After a
complete measuring cycle, the measured value is held independently of the sate of VDI signal.
12
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